Verification of Transaction Level models with Simulation Accelerator

Recently, transaction level modeling (TLM) has been widely referred to in system level design community. Due to lower modeling effort yet higher simulation speed, transaction level models are useful for architectural exploration, algorithmic evaluation, hardware-software partitioning and software development. However, TLM can’t be widely applicable to IP level design phase, because the simulation speed, one of the key merits of TLM, is slowed down where design is progressed. The simulation speed is dependant upon the abstraction level. Higher abstraction level makes faster simulation speed possible. In the IP level design phase, transaction level IP is substituted by lower abstraction level IP such as RTL IP. The conventional method of mixed level simulation is using transaction level simulator and HDL simulator. This two simulator is connected with IPC (inter process communication). But the whole simulation speed of this method is restricted by the speed of HDL simulation. This paper focuses on the methodology to increase the whole simulation speed of mixed level simulation between lower abstraction level IP and transaction level IP. For this acceleration, we approached the hardware-based simulation accelerator. We connected TLM to simulation accelerator instead of HDL simulator.